1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficient load-store ordering.
2. Description of the Relevant Art
Modern microprocessors typically buffer store instructions while waiting for these instructions to retire or be conveyed to a memory subsystem. A store buffer (SB) is a hardware structure configured to buffer store instructions, or write operations. A read-after-write (RAW) hazard may occur when a load instruction, or a read operation, attempts to read a memory location that has been modified by an older (in program order) store instruction that has not yet committed its results to the memory location.
Generally, modern microprocessors implement out-of-order instruction issue and out-of-order instruction execution. Therefore, it is possible for a store instruction younger (in program order) than a particular load instruction to issue for execution before the particular load instruction. A RAW hazard does not exist between this younger store instruction and this particular load instruction. Following, a verification step, such as determining an address match between the two instructions, may not be needed. However, multi-threading and dynamic allocation make the determination more complex.
For a multi-threaded processor, a single-threaded SB may not be replicated by the number of threads in the multi-threaded processor due to on-chip real estate constraints. Also, a multi-threaded processor may not comprise a SB that is divided into sections, wherein each section corresponds to a particular thread. This is an inefficient use of SB entries. For example, one thread may not be utilizing the SB as frequently as a second thread or the one thread may not be executing at all, but the second thread is unable to efficiently utilize the available SB entries since these entries are not assigned to the second thread. Therefore, a multi-threaded processor may utilize a SB with dynamic allocation of its entries. In addition, with dynamic allocation, the SB entries may be used in both single-threaded and multi-threaded modes of operation.
However, a caveat with dynamic allocation is there does not exist a relationship, implied or otherwise, between a SB entry and the order of a corresponding store instruction with respect to other store and load instructions in the pipeline. Accordingly, the determination of load-store RAW hazards becomes more complex as logic needs to ascertain the SB entries that are older (in program order) than a particular load instruction given that an index of the store instructions buffered in the SB does not provide age ordering information.
In view of the above, efficient methods and mechanisms for load-store ordering are desired.